This application claims the priority benefit of Taiwan application serial no. 89114705, filed Jul. 24, 2000.
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a self-aligned silicide layer.
2. Description of the Related Art
When integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. However, resistance of a source/drain region in a metal oxide semiconductor (MOS) transistors increases, and the polysilicon electrodes that form the MOS gates and wiring lines within semiconductor devices introduce undesirable resistance. In order to reduce resistance and RC delay time to improve the operating speed of a device, a self-aligned silicide (salicide) layer is employed. Therefore, a response time or an operating speed of the whole device is increased.
A typical implementation of a silicide layer on a polysilicon electrode or a silicon substrate is known as a self-aligned silicide process. It is employed to reduce semiconductor device resistance. Conventionally, the manufacturing steps for a self-aligned silicide layer are follows as. First, a substrate having an isolation structure is provided, and a gate oxide layer and a doped polysilicon layer are formed on the substrate, respectively. The thickness of the doped polysilicon layer is 1000-3000 xc3x85. The doped polysilicon layer and the gate oxide layer are defined to form a gate, and a lightly doped source/drain region is formed in the substrate by an ion implantation process. A spacer is formed on sidewalls of the gate. The spacer and the gate serve as a mask, and then a heavily doped source/drain region is formed in the substrate by an ion implantation process, wherein the heavily doped source/drain region and the lightly doped source/drain region together form a source/drain region.
A metal layer for forming a silicide layer is deposited over the substrate by sputtering, and then a rapid thermal process is performed. The metal layer only reacts with the gate and the source/drain region to form a silicide layer after performing the thermal process. A portion of the unreacted metal layer is removed by selective wet etching. Since the whole process of forming the silicide layer does not require a photolithography step, the silicide layer formed by the above process is called a self-aligned suicide layer.
Because of the isolation structure, the surface of the substrate is uneven. Therefore, the surface of the polysilicon layer on the substrate is uneven, and the top surface of the subsequently formed gate is also uneven. The thickness of the metal layer on the gate is not uniform, and voids are easily formed between the metal layer and the polysilicon layer. Due to the voids, the contact area between the metal layer and the top surface of the gate is decreased; thus, the number of the nucleation sites is decreased. By the reduction of the nucleation sites, quality of the subsequently formed silicide layer is degraded. As a consequence, sheet resistance of the silicide layer is increased, and the reactivity and the uniformity of thickness of the silicide layer are both affected. Additionally, the performance of the gate is degraded.
Accordingly, the present invention provides a method for forming a self-aligned silicide layer. The method can improve reactivity and uniformity of thickness of the silicide layer, and reduce sheet resistance of the silicide layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a self-aligned silicide layer. A gate with a planar top surface is formed to improve reactivity and uniformity of thickness of the silicide formed in the subsequent process, such that the sheet resistance of the silicide layer is reduced. The formation of a self-aligned silicide layer is described as follows. A gate oxide layer is formed on a substrate, and a polysilicon layer is formed on the gate oxide layer. Then, the polysilicon layer is planarized by chemical mechanical polishing. The polysilicon layer and the gate oxide layer are defined to form a gate with a planar top surface. Finally, a silicide layer is formed on the planar top surface of the gate.
The feature of this invention is the formation of a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.